1FEATURES

23• No special start-up sequence required

between clock/data and /PD pins. Input signal

(clock and data) can be applied either before

or after the device is powered

• Support Spread Spectrum Clocking up to

100kHz frequency modulation and deviations

of ±2.5% center spread or -5% down spread

• Input Clock Detection feature will pull all

LVDS pairs to logic low when input clock is

missing and when /PD pin is logic high

• 18 to 68 MHz shift clock support

• Best-in-Class Setup and Hold Times on

TxINPUTs

• Tx power consumption < 130 mW (typ) at

65MHz Grayscale

• 40% Less Power Dissipation than BiCMOS

Alternatives

• Tx Power-down mode < 60μW (typ)

• Supports VGA, SVGA, XGA and Dual Pixel

SXGA.

• Narrow bus reduces cable size and cost

• Up to 1.8 Gbps throughput

• Up to 227 Megabytes/sec bandwidth

• 345 mV (typ) swing LVDS devices for low EMI

• PLL requires no external components

• Compatible with TIA/EIA-644 LVDS standard

• Low profile 56-lead TSSOP package

• Improved replacement for:

– SN75LVDS83, DS90C383A

DESCRIPTION

The DS90C383B transmitter converts 28 bits of

CMOS/TTL data into four LVDS (Low Voltage

Differential Signaling) data streams. A phase-locked

transmit clock is transmitted in parallel with the data

streams over a fifth LVDS link. Every cycle of the

transmit clock 28 bits of input data are sampled and

transmitted. At a transmit clock frequency of 65 MHz,

24 bits of RGB data and 3 bits of LCD timing and

control data (FPLINE, FPFRAME, DRDY) are

transmitted at a rate of 455 Mbps per LVDS data

channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90C383B transmitter can

be programmed for Rising edge strobe or Falling

edge strobe through a dedicated pin. A Rising edge

or Falling edge strobe transmitter will interoperate

with a Falling edge strobe Receiver (DS90CF386)

without any translation logic.

This chipset is an ideal means to solve EMI and

cable size problems associated with wide, high speed

TTL interfaces.