Function, Pinout, and Drive Compatible

With FCT and F Logic

Reduced VOH (Typically = 3.3 V) Version of

Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

64-mA Output Sink Current

32-mA Output Source Current

Independent Register for A and B Buses

Multiplexed Real-Time and Stored Data

Transfer

3-State Outputs

description

The CY74FCT652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the input bus or from the internal storage registers. GAB and GBA

inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time or

stored-data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in

a multiplexer during the transition between stored and real-time data. A low input level selects real-time data,

and a high input level selects stored data.

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions

of the appropriate clock (CPAB or CPBA) inputs, regardless of the select or enable levels of the control pins.

When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal

D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its

input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus

lines remains at its last state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.