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CY74FCT2652CTQCT中文资料

厂家型号

CY74FCT2652CTQCT

文件大小

312.31Kbytes

页面数量

13

功能描述

8-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

总线收发器 Octal Bus Xceiver and Reg

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

CY74FCT2652CTQCT数据手册规格书PDF详情

Function and Pinout Compatible With FCT

and F Logic

25-Ω Output Series Resistors Reduce

Transmission-Line Reflection Noise

Reduced VOH (Typically = 3.3 V) Versions

of Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

12-mA Output Sink Current

15-mA Output Source Current

Independent Register for A and B Buses

Multiplexed Real-Time and Stored Data

Transfer

3-State Outputs

description

The CY74FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for

multiplexed transmission of data directly from the input bus or from the internal storage registers. Control (GAB

and GBA) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time

or stored data transfer.

The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during

transition between stored and real-time data. A low input level selects real-time data, and a high level selects

stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high

transitions at the appropriate clock (CPAB or CPBA) inputs, regardless of levels at the select- or enable-control

inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using

the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output

reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each

set of bus lines remains at its last state.

On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2652T

can replace the CY74FCT652T to reduce noise in existing designs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

CY74FCT2652CTQCT产品属性

  • 类型

    描述

  • 型号

    CY74FCT2652CTQCT

  • 功能描述

    总线收发器 Octal Bus Xceiver and Reg

  • RoHS

  • 制造商

    Fairchild Semiconductor

  • 逻辑类型

    CMOS

  • 逻辑系列

    74VCX

  • 每芯片的通道数量

    16

  • 输入电平

    CMOS

  • 输出电平

    CMOS

  • 输出类型

    3-State

  • 高电平输出电流

    - 24 mA

  • 低电平输出电流

    24 mA

  • 传播延迟时间

    6.2 ns

  • 电源电压-最大

    2.7 V, 3.6 V

  • 电源电压-最小

    1.65 V, 2.3 V

  • 最大工作温度

    + 85 C

  • 封装/箱体

    TSSOP-48

  • 封装

    Reel

更新时间:2025-10-18 8:30:00
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