Function, Pinout, and Drive Compatible

With FCT and F Logic

Reduced VOH (Typically = 3.3 V) Versions of

Equivalent FCT Functions

Edge-Rate Control Circuitry for

Significantly Improved Noise

Characteristics

Ioff Supports Partial-Power-Down Mode

Operation

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Matched Rise and Fall Times

Fully Compatible With TTL Input and

Output Logic Levels

CY54FCT163T

– 32-mA Output Sink Current

– 12-mA Output Source Current

CY74FCT163T

– 64-mA Output Sink Current

– 32-mA Output Source Current

description

The ’FCT163T devices are high-speed

synchronous modulo-16 binary counters. They

are synchronously presettable for application in

programmable dividers. These devices have two

types of count-enable (CEP and CET) inputs, plus a terminal-count (TC) output for versatility in forming

synchronous multistaged counters. The ’FCT163T devices have a synchronous-reset (SR) input that overrides

counting and parallel loading, and allows the outputs to be reset simultaneously on the rising edge of the clock.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow through the device when it is powered down.