1 Features

• Active current balancing between paralleled

phases sharing a single PWM input

• Peak continuous current: 90-A

• System efficiency: > 95% at 30-A

• High-frequency operation: 1.25-MHz

• Diode emulation function to enable efficiency

discontinuous conduction mode (DCM) operation

• Temperature compensated bi-directional current

sense

• Analog temperature output

• Fault monitoring

• PWM signal compatible: 3.3 V and 5 V

• Tri-state PWM input

• Integrated bootstrap switch

• Optimized dead-time for shoot-through protection

• High-density industry common QFN 5-mm x 6-mm

footprint

• Ultra-low inductance package

• System-optimized PCB footprint

• Thermally enhanced topside cooling

• RoHS compliant - lead-free terminal plating

• Halogen free

2 Applications

• Multiphase synchronous buck converters

– Greater than 500-A

– High-frequency

• Memory and graphic cards

• Data center and network switches

• Campus and branch switches

• Core and edge routers

• Hardware accelerator cards

• High-performance CPU/ASIC/FPGA power

3 Description

The CSD95430RRB NexFET™ power stage is a

highly optimized design for use in a high-power, highdensity

synchronous buck converter. This product

integrates the driver IC and power MOSFETs to

complete the power stage switching function. This

combination produces high-current, high-efficiency,

and high-speed switching capability in a small 5-mm ×

6-mm outline package. It also integrates the accurate

current sensing and temperature sensing functionality

to simplify system design and improve accuracy. In

addition, the PCB footprint has been optimized to help

reduce design time and simplify the completion of the

overall system design. This power stage features an

active current balance feature which allows multiple

power stages to be paralleled off a single PWM input.

This enables phase multiplication for very high current

applications without the need for a similarly high

phase count controller. The active current balance

ensures that the multiplied phases share current

evenly so no significant derating of current capability

is needed when paralleling phases.