1 Features

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 1: –40°C to +125°C

Ambient Operating Temperature Range

– Device Human-Body Model (HBM) ESD

Classification Level 2

– Device Charged-Device Model (CDM) ESD

Classification Level C5

• Available in the small 1.45-mm2

package (DRY) With 0.5-mm Pitch

• Supports 5-V VCC Operation

• Over-voltage tolerant inputs accept

voltages to 5.5 V

• Provides down translation to VCC

• Max tpd of 3.7 ns at 3.3 V

• Low power consumption, 10-μA Max ICC

• ±24-mA Output drive at 3.3 V

• Ioff supports live insertion, partial-power-down

mode, and back-drive protection

• Latch-up performance exceeds 100 mA

Per JESD 78, Class II

2 Applications

• Qualified for Automotive Applications

• Increase digital signal drive strength

• Redrive up to 100 MHz square wave signals

• Enable or disable a digital signal with highimpedance

off state

3 Description

This bus buffer gate is designed for 1.65-V to 5.5-V

VCC operation.

The SN74LVC1G125-Q1 device is a single line driver

with a 3-state output. The output is disabled when the

output-enable ( OE) input is high.

The CMOS device has high output drive while

maintaining low static power dissipation over a broad

VCC operating range.

The SN74LVC1G125-Q1 device is available in a

variety of packages including the small DRY package

with a body size of 1.45 mm × 1.00 mm.