1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1: -40°C to +125°C

– Device HBM ESD classification level 2

– Device CDM ESD classification level C4B

• Available in wettable flank QFN package

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2V to 1.8V

• 1.5V to 2.5V

• 1.8V to 3.3V

• 3.3V to 5.0V

– Down translation:

• 5.0V, 3.3V, 2.5V to 1.8V

• 5.0V, 3.3V to 2.5V

• 5.0V to 3.3V

• Up to 150Mbps with 5V or 3.3V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Synchronize digital signals to clock

• Use fewer inputs to monitor signals

• Convert a switch to a toggle

3 Description

The SN74LV8T273-Q1 contains eight positive-edgetriggered

D-type flip-flops with a direct active low clear

( CLR) input.

Information at the data (D) inputs meeting the setup

time requirements is transferred to the Q outputs on

the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not related directly to the transition time of the

positive-going pulse. When CLK is at either the high

or low level, the D input has no effect at the output.

The input is designed with a reduced threshold circuit

to support up translation when the supply voltage

is larger than the input voltage. Additionally, the 5V

tolerant input pins enable down translation when the

input voltage is larger than the supply voltage. The

output level is always referenced to the supply voltage

(VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS

levels.