位置:CDCVF855PWR > CDCVF855PWR详情
CDCVF855PWR中文资料
CDCVF855PWR数据手册规格书PDF详情
FEATURES
· Spread-Spectrum Clock Compatible
· Operating Frequency: 60 MHz to 220 MHz
· Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200
MHz)
· Low Static Phase Offset: ±50 ps
· Low Jitter (Period): ±60 ps (±30 ps at 200 MHz)
· 1-to-4 Differential Clock Distribution (SSTL2)
· Best in Class for VOX = VDD/2 ±0.1 V
· Operates From Dual 2.6-V or 2.5-V Supplies
· Available in a 28-Pin TSSOP Package
· Consumes < 100-mA Quiescent Current
· External Feedback Pins (FBIN, FBIN) Are Used
to Synchronize the Outputs to the Input
Clocks
· Meets/Exceeds JEDEC Standard (JESD82-1)
For DDRI-200/266/333 Specification
· Meets/Exceeds Proposed DDRI-400
Specification (JESD82-1A)
· Enters Low-Power Mode When No CLK Input
Signal Is Applied or PWRDWN Is Low
APPLICATIONS
· DDR Memory Modules (DDR400/333/266/200)
· Zero-Delay Fan-Out Buffer
DESCRIPTION
The CDCVF855 is a high-performance, low-skew,
low-jitter, zero-delay buffer that distributes a
differential clock input pair (CLK, CLK) to 4
differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled
by the clock inputs (CLK, CLK), the feedback clocks
(FBIN, FBIN), and the analog power input (AVDD).
When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all
outputs are disabled to a high-impedance state
(3-state) and the PLL is shut down (low-power
mode). The device also enters this low-power mode
when the input frequency falls below a suggested
detection frequency that is below 20 MHz (typical 10
MHz). An input frequency-detection circuit detects
the low-frequency condition and, after applying a
>20-MHz input signal, this detection circuit turns the
PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off
and bypassed for test purposes. The CDCVF855 is
also able to track spread-spectrum clocking for
reduced EMI.
Because the CDCVF855 is based on PLL circuitry, it
requires a stabilization time to achieve phase-lock of
the PLL. This stabilization time is required following
power up. The CDCVF855 is characterized for both
commercial and industrial temperature ranges.
CDCVF855PWR产品属性
- 类型
描述
- 型号
CDCVF855PWR
- 功能描述
时钟驱动器及分配 2.5V Ph Lock Loop DDR Clock Driver
- RoHS
否
- 制造商
Micrel
- 1
4
- 输出类型
Differential
- 最大输出频率
4.2 GHz
- 电源电压-最小
5 V
- 最大工作温度
+ 85 C
- 封装/箱体
SOIC-8
- 封装
Reel
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI/德州仪器 |
25+ |
TSSOP28 |
32360 |
TI/德州仪器全新特价CDCVF855PWR即刻询购立享优惠#长期有货 |
|||
TI(德州仪器) |
24+ |
TSSOP28 |
2317 |
只做原装,提供一站式配单服务,代工代料。BOM配单 |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10000 |
||||
TI |
24+ |
TSSOP28 |
5000 |
全现原装公司现货 |
|||
TI |
16+ |
TSSOP |
10000 |
原装正品 |
|||
Texas Instruments |
24+ |
28-TSSOP |
56200 |
一级代理/放心采购 |
|||
TI(德州仪器) |
2447 |
TSSOP-28 |
315000 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
TI |
25+ |
SSOP-28 |
2000 |
就找我吧!--邀您体验愉快问购元件! |
|||
TI(德州仪器) |
2021+ |
TSSOP-28 |
499 |
||||
TI/德州仪器 |
24+ |
TSSOP-28 |
9600 |
原装现货,优势供应,支持实单! |
CDCVF855PWR 资料下载更多...
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