位置:CDCLVP2104RHDR > CDCLVP2104RHDR详情

CDCLVP2104RHDR中文资料

厂家型号

CDCLVP2104RHDR

文件大小

807.83Kbytes

页面数量

32

功能描述

CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer

时钟缓冲器 Low Jtr Dual

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

CDCLVP2104RHDR数据手册规格书PDF详情

1 Features

1• Dual 1:4 Differential Buffer

• Two Clock Inputs

• Universal Inputs Can Accept LVPECL, LVDS,

LVCMOS/LVTTL

• Eight LVPECL Outputs

• Maximum Clock Frequency: 2 GHz

• Maximum Core Current Consumption: 78 mA

• Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range

• 2.375-V to 3.6-V Device Power Supply

• Maximum Propagation Delay: 450 ps

• Maximum 15 ps Within Bank Output Skew

• LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

• Industrial Temperature Range: –40°C to +85°C

• Supports 105°C PCB Temperature (Measured

with a Thermal Pad)

• Available in 5-mm × 5-mm, 28-Pin VQFN (RHD)

Package

• ESD Protection Exceeds 2000 V (HBM)

2 Applications

• Wireless Communications

• Telecommunications/Networking

• Medical Imaging

• Test and Measurement Equipment

3 Description

The CDCLVP2104 is a highly versatile, low additive

jitter buffer that can generate eight copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS

inputs for a variety of communication applications. It

has a maximum clock frequency up to 2 GHz. Each

buffer block consists of one input that feeds two

LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 15 ps,

making the device a perfect choice for use in

demanding applications.

The CDCLVP2104 clock buffer distributes two clock

inputs (IN0, IN1) to eight pairs of differential LVPECL

clock outputs (OUT0, OUT7) with minimum skew for clock distribution. Each buffer block consists of one

input that feeds two LVPECL clock outputs. The

inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP2104 is specifically designed for driving

50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) must be applied to the unused negative

input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP2104 is characterized for operation from

–40°C to +85°C and is available in a 5-mm × 5-mm, QFN-28 package.

CDCLVP2104RHDR产品属性

  • 类型

    描述

  • 型号

    CDCLVP2104RHDR

  • 功能描述

    时钟缓冲器 Low Jtr Dual

  • 1

    4 Uni-to-LVPECL Bfr

  • RoHS

  • 制造商

    Texas Instruments

  • 输出端数量

    5

  • 最大输入频率

    40 MHz

  • 电源电压-最大

    3.45 V

  • 电源电压-最小

    2.375 V

  • 最大工作温度

    + 85 C

  • 最小工作温度

    - 40 C

  • 封装/箱体

    LLP-24

  • 封装

    Reel

更新时间:2026-2-1 13:38:00
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TI
1725+
VQFN28
7500
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TI
三年内
1983
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24+
VQFN28
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订货中主营TI
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特价全新原装公司现货