Low Output Skew, Low Pulse Skew for

Clock-Distribution and Clock-Generation

Applications

TTL-Compatible Inputs and

CMOS-Compatible Outputs

Distributes One Clock Input to Eight

Outputs

– Four Same-Frequency Outputs

– Four Half-Frequency Outputs

Distributed VCC and Ground Pins Reduce

Switching Noise

High-Drive Outputs (–48-mA IOH,

48-mA IOL)

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Plastic

Small-Outline (DW)

description

The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring

synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs

switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the

frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the

Q outputs toggle on low-to-high transitions at CLK. Taking CLR low asynchronously resets the Q outputs to the

low level. When OE is high, the outputs are in the high-impedance state.

The CDC337 is characterized for operation from –40°C to 85°C.