4.5-V to 5.5-V VCC Operation

Input Latches for BCD Code Storage

Blanking Capability

Phase Input for Complementing Outputs

Fanout (Over Temperature Range)

– Standard Outputs – 10 LSTTL Loads

Balanced Propagation Delay and Transition

Times

Significant Power Reduction, Compared to

LSTTL Logic ICs

Direct LSTTL Input Logic Compatibility,

VIL = 0.8 V Maximum, VIH = 2 V Minimum

CMOS Input Compatibility, II ≤ 1 μA at VOL,

VOH

description/ordering information

The CD74HCT4543 high-speed silicon-gate is a BCD-to-7 segment latch/decoder/driver designed primarily for

directly driving liquid-crystal displays. While the latch enable (LD) is low, the latches are enabled to store the

BCD inputs. When the latch enable is high, the latches are disabled, making the outputs transparent to the BCD

inputs. The device has an active-high blanking input (BI) and a phase input (PH) to which a square wave is

applied for liquid-crystal applications. This square wave also is applied to the backplane of the liquid-crystal

display.