Features

• Four Operating Modes

- Shift Right, Shift Left, Hold and Reset

• Synchronous Parallel or Serial Operation

• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,

TA = 25oC

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The ’HC194 and CD74HCT194 are 4-bit shift registers with

Asynchronous Master Reset (MR). In the parallel mode (S0

and S1 are high), data is loaded into the associated flip-flop

and appears at the output after the positive transition of the

clock input (CP). During parallel loading serial data flow is

inhibited. Shift left and shift right are accomplished

synchronously on the positive clock edge with serial data

entered at the shift left (DSL) serial input for the shift left

mode, and at the shift right (DSR) serial input for the shift

right mode. Clearing the register is accomplished by a Low

applied to the Master Reset (MR) pin.