Qualified for Automotive Applications

Select One of Eight Data Outputs Active

Low

I/O Port or Memory Selector

Three Enable Inputs to Simplify Cascading

Typical Propagation Delay of 13 ns at

VCC = 5 V, CL = 15 pF, TA = 25
C

Fanout (Over Temperature Range)

− Standard Outputs . . . 10 LSTTL Loads

− Bus Driver Outputs . . . 15 LSTTL Loads

Balanced Propagation Delay and Transition

Times

Significant Power Reduction Compared to

LSTTL Logic ICs

2-V to 6-V VCC Operation

High Noise Immunity; NIL or NIH = 30% of

VCC, VCC = 5 V

description/ordering information

The CD74HC138 is a high-speed silicon-gate CMOS

decoder well suited to memory address decoding or

data routing applications. This circuit features low

power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky

TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs

determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders.

The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.