1 Features

• Buffered inputs

• Typical propagation delay

– 6ns at VCC = 5V, TA = 25°C, CL = 50pF

• Exceeds 2kV ESD protection MIL-STD-883,

method 3015

• SCR-latchup-resistant CMOS process and circuit

design

• Speed of bipolar FAST™/AS/S with significantly

reduced power consumption

• Balanced propagation delays

• AC types feature 1.5V to 5.5V operation and

balanced noise immunity at 30% of the supply

• ±24mA output drive current

– Fanout to 15 FAST™ ICs

– Drives 50Ω transmission lines

2 Description

The CD74AC251 8-input multiplexers that utilize

the Harris Advanced CMOS Logic technology. This

multiplexer features both true (Y) and complement

Y) outputs as well as an Output Enable (OE) input.

The OE must be at a LOW logic level to enable this

device. When the OE input is HIGH, both outputs are

in the high-impedance state. When enabled, address

information on the data select inputs determines

which data input is routed to the Y and Y outputs.