1 Features

Processor Cores:

• Dual 64-bit Arm® Cortex®-A53 microprocessor

subsystem up to 1.25GHz

– Dual-core Cortex-A53 with 256KB L2 Cache

– Each A53 core has 32KB L1 DCache and 32KB

L1 ICache

Memory Subsystem:

• 160KB of Shared On-Chip SRAM (OCSRAM)

• DDR Subsystem (DDRSS)

– Supports LPDDR4, DDR4 memory types

– 16-bit data bus

– Supports speeds up to 1600MT/s

– Max DDR4 addressing range of 4GB

– Max LPDDR4 addressing range of 2GB

Multimedia:

• Display Subsystem

– Single display support

– Up to 1920x1080 @ 60fps

– Supported with independent PLL

– MIPI® DSI (4 lanes DPHY) or DPI (24-bit RGB

LVCMOS)

Security:

• Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Trusted Execution Environment (TEE) supported

– Arm TrustZone® based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

• Dedicated Security Controller and dedicated

security DMA & IPC subsystem for isolated

processing

• Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

– Supports cryptographic cores

• AES – 128-/192-/256-bit key sizes

• SHA2 – 224-/256-/384-/512-bit key sizes

• DRBG with true random number generator

• SM3 and SM4

• Public Key Engine (PKE) to Assist in

RSA/ECC processing for secure boot

• Debugging security

– Secure software controlled debug access

– Security aware debugging

High Speed Interfaces:

• Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Priority based flow control

– Packet Classifier based on ALE engine with 64

classifiers

– Time sensitive networking (TSN) support

– H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

• 2× USB 2.0 Dual-Role Device (DRD) Subsystems

(USBSS)

– Port configurable as USB host or USB device

– USB device: High-speed (480Mbps), and Fullspeed

(12Mbps)

– USB host: High-speed (480Mbps), Full-speed

(12Mbps), and Low-speed (1.5Mbps)

– xHCI 1.1 compatible

General Connectivity:

• 8x Universal Asynchronous Receiver-Transmitters

(UARTs)

– All instances Support RTS and CTS Flow

Control

– Supports RS-485 external transceiver auto flow

control

• 4x Serial Peripheral Interface (SPI) controllers

• 5x Inter-Integrated Circuit (I2C) ports

• 3x Multichannel Audio Serial Ports (McASPs)

– Transmit and Receive clocks up to 50MHz

– Up to 4/6/16 Serial Data Pins across 3x

McASPs with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and similar formats

– Supports Digital Audio Interface Transmission

(SPDIF, IEC60958-1, and AES-3 formats)

– FIFO buffers for Transmit and Receive

(256Bytes)

– Support for audio reference output clock

• 3x enhanced PWM modules (ePWM)

• 3x enhanced Quadrature Encoder Pulse modules

(eQEP)

• 3x enhanced Capture modules (eCAP)

• General-Purpose I/O (GPIO), most LVCMOS I/O

can be configured as GPIO

– 4 banks supported for dual-voltage (1.8V/3.3V)

and the rest single-voltage (1.8V) LVCMOS I/O

banks

• 3x Controller Area Network (CAN) with optional

CAN-FD support

– Conforms with CAN Protocol 2.0 A, B, and ISO

11898-1

– Full CAN-FD support (up to 64 data bytes)

– Speed up to 8Mbps

• 1x 12-bit Analog-to-Digital Converter (ADC)

– 10 bits of effective resolution (ENOB ≅ 10)

– Up to 2MSPS

– 4x analog inputs (time-multiplexed)

Media and Data Storage:

• 3x Multi-Media Card/Secure Digital® (MMC/SD®)

interface

– 1x 8-bit eMMC interface up to HS200 speed

– 2x 4-bit SD/SDIO interface up to UHS-I

– Compliant with eMMC 5.1, SD 3.01, and SDIO

Version 3.0

• 1× General-Purpose Memory Controller (GPMC)

up to 133MHz

– Flexible 8- and 16-Bit Synchronous or

Asynchronous Memory Interfaces with up to

four Chip Selects

– Supports 16-bit Muxed Address/Data schemes

(AD, AAD)

– Uses BCH code to support 4-, 8-, or 16-bit ECC

– Uses Hamming code to support 1-bit ECC

– Error Locator Module (ELM)

• OSPI/QSPI with DDR / SDR support

– Support for Serial NAND and Serial NOR Flash

devices

– 4GBytes memory address support

Power Management:

• Active power management features such as auto

clock gating, power gating, and dynamic frequency

scaling

• Several low-power features supported

• Low-Power Modes

– RTC Only

– RTC + IO + DDR

– DeepSleep

– Standby

Boot Options:

• UART

• OSPI/QSPI Flash

• GPMC NAND Flash

• SD Card

• eMMC

• USB (host) Mass storage

• USB (device) boot from external host (DFU mode)

Technology / Package:

• 16-nm Technology

• 11.9mm × 11.9mm, 0.5mm VCA, 373-pin FCCSP

BGA package (ANB)

2 Applications

• Human Machine Interface (HMI)

• Medical - patient monitoring

• Building automation

• EV charging stations

• Solar energy

• Energy Infrastructure (Smart Meter & Solar Gateway)

• Mobile/Industrial printers

3 Description

The low-cost & performance optimized AM62L family of application processors are built for Linux® application

development. With scalable Arm® Cortex®-A53 core performance and embedded features such as: Multimedia

DSI/DPI support, integrated ADC on chip, advanced lower power management modes, and extensive security

options for IP protection with the built-in security features.

The AM62Lx devices includes an extensive set of peripherals that make it a well-suited general-purpose device

for a broad range of industrial applications while offering intelligent features and optimized power architecture as

well. In addition, the extensive set of peripherals included in AM62Lx enables system-level connectivity, such as:

USB, MMC/SD, OSPI, CAN-FD and an ADC.