1 Features

1• Quad Channel

• 12-Bit Resolution

• Single Supply: 1.8 V

• Serial LVDS Interface

• Flexible Input Clock Buffer with Divide-by-1, -2, -4

• SNR = 70.2 dBFS, SFDR = 87 dBc at

fIN = 70 MHz

• Ultra-Low Power Consumption:

– 98 mW/Ch at 125 MSPS

• Channel Isolation: 105 dB

• Internal Dither and Chopper

• Support for Multi-Chip Synchronization

• Pin-to-Pin Compatible with 14-Bit Version

• Package: VQFN-56 (8 mm × 8 mm)

2 Applications

• Multi-Carrier, Multi-Mode Cellular Base Stations

• Radar and Smart Antenna Arrays

• Munitions Guidance

• Motor Control Feedback

• Network and Vector Analyzers

• Communications Test Equipment

• Nondestructive Testing

• Microwave Receivers

• Software-Defined Radios (SDRs)

• Quadrature and Diversity Radio Receivers

3 Description

The ADC342x are a high-linearity, ultra-low power,

quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices

are designed specifically to support demanding, high

input frequency signals with large dynamic range

requirements. An input clock divider allows more flexibility for system clock architecture design and the

SYSREF input enables complete system

synchronization. The ADC342x family supports serial

low-voltage differential signaling (LVDS) in order to

reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS

interface is two-wire, where each ADC data are

serialized and output over two LVDS pairs. An

internal phase-locked loop (PLL) multiplies the

incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from

each channel. In addition to the serial data streams,

the frame and bit clocks are also transmitted as

LVDS outputs.