1FEATURES

2• Single +3.3V Supply Operation

• Internal Sample-and-Hold

• Internal or External Reference

• Outputs 2.4V to 3.6V Compatible

• Power Down Mode

• Duty Cycle Stabilizer

• Pin Compatible with ADC12DL040,

ADC12DL065, ADC12DL066

APPLICATIONS

• Instrumentation

• Communications Receivers

• Sonar/Radar

• xDSL, Cable Modems

KEY SPECIFICATIONS

• Resolution: 12 Bits

• Max Conversion Rate: 80 MSPS

• DNL: ±0.4 LSB (typ)

• SNR (f IN=40MHz): 69 dB (typ)

• SNR (fIN=200MHz): 67 dB(typ)

• SFDR (fIN=40MHz): 82 dB (typ)

• SFDR (fIN=200MHz): 81 dB (typ)

• Power Consumption

– Operating: 447 mW (typ)

– Power Down Mode: 50 mW (typ)

DESCRIPTION

The ADC12DL080 is a dual, low power monolithic

CMOS analog-to-digital converter capable of

converting analog input signals into 12-bit digital

words at 80 Megasamples per second (MSPS). This

converter uses a differential, pipeline architecture with

digital error correction and an on-chip sample-and- hold circuit to minimize power consumption while

providing excellent dynamic performance and a 600

MHz Full Power Bandwidth. Operating on a single

+3.3V power supply, the ADC12DL080 achieves 11.0

effective bits at Nyquist and consumes just 447mW at

80 MSPS. The Power Down feature reduces power

consumption to 50 mW.

The differential inputs provide a full scale differential

input swing equal to 2 times VREF with the possibility

of a single-ended input. Full use of the differential

input is recommended for optimum performance.

Duty cycle stabilization and output data format are

selectable. The output data can be set for offset

binary or two's complement.

To ease interfacing to lower voltage systems, the

digital output driver power pins of the ADC12DL080

can be connected to a separate supply voltage in the

range of 2.4V to the analog supply voltage. This

device is available in the 64-lead TQFP package and

will operate over the industrial temperature range of

−40°C to +85°C. An evaluation board is available to

ease the evaluation process.