Features:

® Strobed input latch

® Inhibit contral

u 100% tested for quiescent current at 20 V

® Maximum input current of 1 uA at 18 V

over full package-temperature range;

100 nA at 18 V and 25°C

u Noise margin (over full package temper-

ature range):

1VatVpp= 5V

2VatVpp=10V

25VatVpp=15V

8 5.V, 10-V, ad 15-V parametric ratings

8 Standardized, symmetrical output

characteristics.

® Meets all requirements of JEDEC Tentative -

Standard No. 13B; ‘Standard Specifications

for Description of ‘B* Series CMOS Devices”