1 Features

1• QML-V Qualified, SMD 5962-94555

• Rad-Tolerant: 50 kRad (Si) TID (1)

• Zero to 100% Duty Cycle Control

• Programmable Output Turn-On Delay

• Compatible with Voltage or Current Mode

Topologies

• Practical Operation at Switching Frequencies to

1 MHz

• Four 2-A Totem Pole Outputs

• 10-MHz Error Amplifier

• Undervoltage Lockout (UVLO)

• Low Startup Current – 150 μA

• Outputs Active Low During UVLO

• Soft-Start Control

• Latched Overcurrent Comparator With Full Cycle

Restart

• Trimmed Reference

2 Applications

Power FPGAs

3 Description

The UC1875-SP implements control of a bridge

power stage by phase-shifting the switching of one

half-bridge with respect to the other, allowing

constant frequency pulse-width modulation in

combination with resonant, zero-voltage switching for

high efficiency performance at high frequencies. This

circuit may be configured to provide control in either

voltage or current mode operation, with a separate

overcurrent shutdown for fast fault protection.

A programmable time delay is provided to insert a

dead-time at the turn-on of each output stage. This

delay, providing time to allow the resonant switching

action, is independently controllable for each output

pair (A-B, C-D).

With the oscillator capable of operation at frequencies

in excess of 2 MHz, overall switching frequencies to

1 MHz are practical. In addition to the standard free

running mode, with the CLOCKSYNC pin, the user

may configure these devices to accept an external

clock synchronization signal, or may lock together up

to 5 units with the operational frequency determined

by the fastest device.