1 Features

• Input voltage range:

– Legacy chip: 2.7 V to 10 V (13.5-V absolute

max)

– New chip: 2.5 V to 16 V (18-V absolute max)

• Output voltage range:

– Legacy chip: 1.5 V to 5 V (fixed) and 1.25 V to

5.5 V (adjustable)

– New chip: 1.2 V to 12 V (fixed) and 0.8 V to

14.6 V (adjustable)

• Output current: Up to 250 mA

• Output accuracy:

– Legacy chip: 3 over load and temperature

– New chip: 1 over load and temperature

• Low quiescent current (IQ):

– Legacy chip: 35 μA (typ) with no load

– New chip: 55 μA (typ) with no load

• IQ (disabled state):

– Legacy chip: 10 μA (max)

– New chip: 4 μA (max)

• Dropout voltage (new chip):

– Up to 225 mV (typ) at 250 mA (TPS76650)

• High PSRR (new chip): 46 dB at 1 MHz

• Internal soft-start time (new chip): 750 μs (typical)

• Overcurrent limiting and thermal protection

• Stable with a 2.2-μF or larger capacitor (new chip)

• Open-drain power-good

• Package: 8-pin, 4.9-mm × 6-mm SOIC (D)

2 Applications

• Residential air conditioners

• Body electronics and lighting

• HVAC systems

• Washers and dryers

3 Description

The TPS766 is a low-dropout (LDO) linear voltage

regulator that supports an input voltage range from

2.5 V to 16 V (new chip) and up to 250 mA of load

current. For the new chip, the supported output range

is from 1.2 V to 12 V (fixed version) or from 0.8 V to

14.6 V (adjustable version).

The input voltage range is up to 16 V (new chip),

which makes the device a good choice for operating

from transformer secondary windings and regulated

rails (such as 10 V or 12 V). Additionally, the wide

output voltage range allows the device to generate

the bias voltage for silicon carbide (SiC) gate drivers

and microphones, as well as power microcontrollers

(MCUs) and processors.

Wide bandwidth PSRR performance is greater than

70 dB at 1 kHz and 46 dB at 1 MHz (new chip),

which helps attenuate the switching frequency of

an upstream DC/DC converter and minimizes post

regulator filtering. The new chip supports internal

soft-start circuit mechanism that reduces inrush

current during start-up, thus allowing for smaller input

capacitance.

The legacy chip supports constant quiescent current

across the complete load current range (typically 35

μA for the full range of output current, 0 mA to 250

mA).