1 Features

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2V to 1.8V

• 1.5V to 2.5V

• 1.8V to 3.3V

• 3.3V to 5.0V

– Down translation:

• 5.0V, 3.3V, 2.5V to 1.8V

• 5.0V, 3.3V to 2.5V

• 5.0V to 3.3V

• Up to 150Mbps with 5V or 3.3V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

• Supports defense and aerospace applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

• Enable or disable a digital signal

• Controlling an indicator LED

• Translation between communication modules and

system controllers

3 Description

The SN74LV8T573-EP devices are octal transparent

D-type latches that feature 3-state outputs designed

specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable

for implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the

Q outputs respond to the data (D) inputs. When LE is

low, the outputs are latched to retain the data that was

set up.