1 Features

• Single or dual port MIPI DSI receiver

– Compliant to D-PHY v1.2 and DSI v1.3.1

– Packed 16/18/24/30-bit RGB and 16-bit YCbCr

– Loosely packed 18-bit RGB and 20-bit 4:2:2

– 1 clock lane and 1-4 configurable data lanes

per D-PHY Port

– Up to 2.5 Gbps/lane with skew calibration

– Supports data lane swap and polarity inversion

– Supports both burst and non-burst mode

– SuperFrame Unpacking Capability

– Suitable for 4K at 60Hz video resolution

• FPD-Link IV interface

– Supports 10.8/6.75/3.375Gbps per channel; Up

to 21.6Gbps over dual channels

– Coax/STP interconnect support

– Port Splitting to enable Y-cable interfaces

• Ultra-low latency control channel

– Two I2C up to 1MHz (up to 3.4MHz for local

bus access)

– High speed GPIOs

• Backwards compatible

– 720P 92x and 1080P/2K 94x product families

– ADAS 936, 954, 960, 962, 9702, 9722

deserializers

• Security and diagnostics

– Voltage and temperature monitoring

– Line Fault Detection

– BIST and pattern generation

– CRC and error diagnostics

– Unique ID for counterfeit protection

– ECC on control bits

• Advanced link robustness and EMC control

– Data scrambling

– Spread spectrum clocking generation (SSCG)

• Low power operation

– 1.8V and 1.1V dual power supply

• AEC-Q100 qualified for automotive applications

– AEC-Q100 grade-level 2: −40℃ to +105℃

– 64 pin QFN Wettable flanks 9mm x 9mm

– ISO 10605 and IEC 61000-4-2 ESD compliant

2 Applications

• Automotive displays:

– Central Information Displays (CID)

– Rear Seat Entertainment (RSE)

– Digital instrument clusters

– Head units and HMI modules

– Head Up Display (HUD)

– Rear view and side mirror displays

3 Description

DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV

bridge device. In conjunction with an FPD-Link

IV deserializer, the chipset provides a high-speed

serialized interface over low-cost 50Ω coax or

STP cables. The DS90UB981-Q1 is a D-PHY v1.2

compliant device that serializes a MIPI DSI input

supporting video resolutions including 4K with 30-bit

color depth. The FPD-Link IV interface supports video

and audio data transmission and full duplex control,

including I2C and GPIO data over a single channel or

dual channels. Consolidation of video data and control

over two FPD-Link IV lanes reduces the interconnect

size and weight and simplifies system design. EMI

is minimized by the use of low voltage differential

signaling, data scrambling, SSCG, and randomization.

In backward compatible mode, the devices supports

up to 720p and 1080p resolutions with 24-bit color

depth over a single/dual link. In ADAS compatible

mode, the device is interoperable with 936, 95x, 96x &

97x deserializers supporting resolutions up to 8MP+/

40fps.