1 Features

Processor Cores:

• Up to Quad 64-bit Arm® Cortex®-A53

microprocessor subsystem at up to 1.4 GHz

– Quad-core Cortex-A53 cluster with 512KB L2

shared cache with SECDED ECC

– Each A53 core has 32KB L1 DCache with

SECDED ECC and 32KB L1 ICache with Parity

protection

• Single-core Arm® Cortex®-R5F at up to 800 MHz,

integrated as part of MCU Channel with FFI

– 32KB ICache, 32KB L1 DCache, and 64KB

TCM with SECDED ECC on all memories

– 512KB SRAM with SECDED ECC

• Single-core Arm® Cortex®-R5F at up to 800 MHz,

integrated to support Device Management

– 32KB ICache, 32KB L1 DCache, and 64KB

TCM with SECDED ECC on all memories

Multimedia:

• Display subsystem

– Triple display support over OLDI (LVDS) (1x

OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI

• OLDI-SL (Single Link): up to 1920 x 1080 at

60fps (165-MHZ Pixel Clock)

• OLDI-DL (Dual Link): up to 3840 x 1080 at

60 fps (150-MHz Pixel Clock)

• MIPI® DSI: with 4 Lane MIPI® D-PHY

supports up to 3840 x 1080 at 60 fps (300-

MHz Pixel Clock)

• DPI (24-bit RGB parallel interface): up to

1920 x 1080 at 60 fps (165-MHz pixel clock)

– Four display pipelines with hardware overlay

support. A maximum of two display pipelines

may be used per display.

– Supports safety features such as freeze frame

detection and data correctness check

• 3D Graphics Processing Unit

– IMG BXS-4-64 with 256KB cache

– Up to 50 GFLOPS

– Single shader core

– OpenGL ES3.2 and Vulkan 1.2 API support

• One Camera Serial Interface (CSI-2) Receiver with

4 Lane D-PHY

– MIPI® CSI-2 v1.3 Compliant + MIPI D-PHY 1.2

– Support for 1,2,3 or 4 data lane mode up to 1.5

Gbps per lane

– ECC verification/correction with CRC check +

ECC on RAM

– Virtual Channel support (up to 16)

– Ability to write stream data directly to DDR via

DMA

• Video Encoder/Decoder

– Support for HEVC (H.265) Main profiles at

Level 5.1 High-tier

– Support for H.264 BaseLine/Main/High Profiles

at Level 5.2

– Support for up to 4K UHD resolution

(3840 × 2160)

• Up to 300 MPixels/s operation, with reduced

clocking options available for lower power

applications with lower performance needs

Memory Subsystem:

• Up to 1.09MB of On-chip RAM

– 64KB of On-Chip RAM (OCRAM) with

SECDED ECC, can be divided into smaller

banks in increments of 32KB for as many as

2 separate memory banks

– 256KB of On-Chip RAM with SECDED ECC in

SMS Subsystem

– 176KB of On-Chip RAM with SECDED ECC in

SMS Subsystem for TI security firmware

– 512KB of On-chip RAM with SECDED ECC in

Cortex-R5F MCU Subsystem

– 64KB of On-chip RAM with SECDED ECC in

Device Manager Subsystem

• DDR Subsystem (DDRSS)

– Supports LPDDR4 memory type

– 32-bit data bus with inline ECC

– Supports speeds up to 3200 MT/s

– Max size of 8GB

Functional Safety:

• Functional Safety-Compliant targeted [Industrial]

– Developed for functional safety applications

– Documentation will be available to aid IEC

61508 functional safety system design

– Systematic capability up to SIL 3 targeted

– Hardware Integrity up to SIL 2 targeted

– Safety-related certification

• IEC 61508 by TÜV SÜD planned

• Functional Safety-Compliant targeted [Automotive]

– Developed for functional safety applications

– Documentation will be available to aid ISO

26262 functional safety system design

– Systematic capability up to ASIL D targeted

– Hardware integrity up to ASIL B targeted

– Safety-related certification

• ISO 26262 by TÜV SÜD planned

• AEC - Q100 qualified [Automotive]

Security:

• Secure boot supported

– Hardware-enforced Root-of-Trust (RoT)

– Support to switch RoT via backup key

– Support for takeover protection, IP protection,

and anti-roll back protection

• Trusted Execution Environment (TEE) supported

– Arm TrustZone® based TEE

– Extensive firewall support for isolation

– Secure watchdog/timer/IPC

– Secure storage support

– Replay Protected Memory Block (RPMB)

support

• Dedicated Security Controller with user

programmable HSM core and dedicated security

DMA & IPC subsystem for isolated processing

• Cryptographic acceleration supported

– Session-aware cryptographic engine with ability

to auto-switch key-material based on incoming

data stream

• Supports cryptographic cores

– AES – 128-/192-/256-Bit key sizes

– SHA2 – 224-/256-/384-/512-Bit key sizes

– DRBG with true random number generator

– PKA (Public Key Accelerator) to Assist in

RSA/ECC processing for secure boot

• Debugging security

– Secure software controlled debug access

– Security aware debugging

High-Speed Interfaces:

• Integrated Ethernet switch supporting (total 2

external ports)

– RMII(10/100) or RGMII (10/100/1000)

– IEEE1588 (Annex D, Annex E, Annex F with

802.1AS PTP)

– Clause 45 MDIO PHY management

– Packet Classifier based on ALE engine with

512 classifiers

– Priority based flow control

– Time Sensitive Networking (TSN) support

– Four CPU H/W interrupt Pacing

– IP/UDP/TCP checksum offload in hardware

• Two USB2.0 Ports

– Port configurable as USB host, USB peripheral,

or USB Dual-Role Device (DRD mode)

– Integrated USB VBUS detection

General Connectivity:

• 9x Universal Asynchronous Receiver-Transmitters

(UART)

• 5x Serial Peripheral Interface (SPI) controllers

• 6x Inter-Integrated Circuit (I2C) ports

• 3x Multichannel Audio Serial Ports (McASP)

– Transmit and Receive Clocks up to 50 MHz

– Up to 16/10/6 Serial Data Pins across 3x

McASP with Independent TX and RX Clocks

– Supports Time Division Multiplexing (TDM),

Inter-IC Sound (I2S), and Similar Formats

– Supports Digital Audio Interface Transmission

(SPDIF, IEC60958-1, and AES-3 Formats)

– FIFO Buffers for Transmit and Receive (256

Bytes)

– Support for audio reference output clock

• 3x enhanced PWM modules (ePWM)

• 3x enhanced Quadrature Encoder Pulse modules

(eQEP)

• 3x enhanced Capture modules (eCAP)

• General-Purpose I/O (GPIO), All LVCMOS I/O can

be configured as GPIO

• 4x Controller Area Network (CAN) modules with

CAN-FD support

– Conforms w/ CAN Protocol 2.0 A, B and ISO

11898-1

– Full CAN-FD support (up to 64 data bytes)

– Parity/ECC check for Message RAM

– Speed up to 8 Mbps

Media and Data Storage:

• 3x Multi-Media Card/Secure Digital® (MMC/SD®/

SDIO) interfaces

– 1x 8-bit eMMC interface up to HS400 speed

– 2x 4-bit SD/SDIO interfaces up to UHS-I

– Compliant with eMMC 5.1, SD 3.0, and SDIO

Version 3.0

• 1× General-Purpose Memory Controller (GPMC)

up to 133 MHz

– Flexible 8- and 16-bit Asynchronous Memory

Interface with up to four Chip (22-bit address)

Selects (NAND, NOR, Muxed-NOR, and

SRAM)

– Uses BCH code to support 4-, 8-, or 16-bit ECC

– Uses Hamming code to support 1-bit ECC

– Error Locator Module (ELM)

• Used with the GPMC to locate addresses

of data errors from syndrome polynomials

generated using a BCH algorithm

• Supports 4-, 8-, and 16-bit per 512-

Byte block error location based on BCH

algorithms

• OSPI/QSPI with DDR / SDR support

– Support for Serial NAND and Serial NOR Flash

devices

– 4GBytes memory address support

– XIP mode with optional on-the-fly encryption

Power Management:

• Low-power modes supported by Device Manager:

– Partial IO support for CAN/GPIO/UART wakeup

– I/O Only + DDR in Self Refresh for Suspend to

RAM

– DeepSleep

– MCU Only

– Standby

– Dynamic frequency scaling

Optimal Power Management Solution:

• Recommended TI Power Management ICs (PMIC)

– Supports up to Automotive ASIL-B functional

safety when powering the AEC – Q100

qualified AM62P-Q1 device

– Supports up to SIL-2 functional safety industrial

applications when powering the AM62P device

– Companion PMIC is specially designed to meet

power supply requirements

– Flexible mapping and factory programmed

configurations to support different use cases

Boot Options:

• UART

• I2C EEPROM

• OSPI/QSPI Flash

• GPMC NOR/NAND Flash

• SD Card

• eMMC

• USB (host) Mass storage

• USB (device) boot from external host (DFU mode)

• Ethernet

Technology / Package:

• 16-nm FinFET technology

• 17 mm x 17 mm, 0.65-/0.8-mm pitch with VCA,

466-pin FCBGA

2 Applications

• Industrial Human Machine Interfaces (HMI)

• Appliance User Interface and Connectivity

• Medical Equipment

• Automotive Instrument Clusters

• Automotive Display

• Augmented Reality HUD

3 Description

The AM62Px (P = Plus) is an extension of the existing Sitara™ AM62x low-cost family of application processors

built for high-performance embedded 3D display applications. Scalable Arm® Cortex®-A53 performance and

embedded features, such as: multi-screen high-definition display support, 3D-graphics acceleration, 4K video

acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automotive and

industrial applications, including automotive digital instrumentation, automotive displays, industrial HMI, and

more.

Key features and benefits:

• Focus on innovation and fast development with Linux® and Android™ SDKs accompanied with real-time

functional safety and security SDKs.

• Address next wave of HMI designs with new generation of 3D GPU and 4K video acceleration.

• Enhance your design connectivity with an extensive set of automotive and high-speed IOs, including: 4x

CAN-FD, 3-port Gigabit Ethernet switch (two external ports) with TSN support, and two USB2.0 ports.

• Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).

• Provides intelligent features, such as: facial recognition and touchless HMI with Arm® Cortex®-A53 CPUs

and open-source AI software and tools

The AM62Px processors comply with the AEC - Q100 automotive standard and support industrial-grade. ASIL-B

and SIL-2 functional safety requirements can be addressed using an integrated Arm Cortex-R5F core and

dedicated peripherals, which can all be isolated from the rest of the processor.

Products in the AM62Px processor family:

AM62P-Q1 – Automotive digital instrumentation SoC with scalable Arm Cortex-A53 performance, multi highdefinition

display support, 3D GPU and 4K video acceleration.

Featured design resources:

• Hardware Evaluation Module (EVM) - SK-AM62P-LP

• Software Development Kit (SDK) - PROCESSOR-SDK-AM62P

• Linux Academy