1 Features

• Qualified for automotive applications

– AEC-Q100 grade 1: –40 to 125°C TA

• Integrated avalanche rated MOSFETs

– Designed and qualified for reliability for

dielectric withstand testing (Hi-Pot)

• IAVA = 2-mA for 5-s pulses, 1-mA for 60-s

pulses

• VHIPOT, 5-s = 4300-V with Rseries > 1.83-MΩ

• VHIPOT, 5-s = 2850-V with Rseries > 1.1-MΩ

– 600-V standoff voltage

– RON = 65-Ω (TJ = 25°C)

– IOFF = 1-μA at 500-V (TJ = 105°C)

• Low primary side supply current

– 5-mA single channel, 9-mA two channel ON

state current

• Functional Safety Capable

– Documentation available to aid in ISO 26262

and IEC 61508 system design

• Robust isolation barrier:

– > 26 year projected lifetime at 1000-VRMS /

1500-VDC working voltage

– Isolation rating, VISO, up to 3750-VRMS / 5300-

VDC

• SOIC 11-pin (DWQ) package with wide pins for

improved thermal performance

– Creepage and clearance ≥ 8-mm (primarysecondary)

– Creepage and clearance ≥ 3-mm (across

switch terminals)

• Safety-related certifications

– (Planned) DIN VDE V 0884-11:2017-01

– (Planned) UL 1577 component recognition

program

2 Applications

• Solid state relay

• Hybrid, electric, and power train systems

• Battery Management Systems (BMS)

• Energy Storage Systems (ESS)

• Solar energy

• Onboard charger

• EV charging infrastructure

• See also the TI Reference Designs related to

these applications.

3 Description

The TPSI2072-Q1 is a two channel isolated solid

state relay designed for high voltage automotive

and industrial applications. The TPSI2072-Q1 uses

TI's high reliability capacitive isolation technology

in combination with internal back-to-back MOSFETs

to form a completely integrated solution requiring

no secondary side power supply. The TPSI2072-

Q1 improves system reliability as TI's capacitive

isolation technology does not suffer from mechanical

wearout or photo degradation failure modes common

in mechanical relay and photo relay components.

The primary side of the device is powered by only

9 mA of input current and incorporates fail-safe EN1

and EN2 pins preventing any possibility of back

powering the VDD supply. In most applications, the

VDD pin of the device should be connected to a

system supply between 4.5 V–20 V and the EN1

and EN2 pins of the device should be driven by a

GPIO output with logic HI between 2.1 V–20 V. In

other applications, the VDD, EN1, and EN2 pins could

be driven together directly from the system supply or

from a GPIO output.

Each channel on the secondary side consists of backto-

back MOSFETs with a standoff voltage of +/-600

V from SM to S1 and SM to S2. The TPSI2072-

Q1 MOSFET's avalanche robustness and thermally

conscious package design allow it to robustly support

system level dielectric withstand testing (HiPot) and

DC fast charger surge currents of up to 2 mA without

requiring any external components.