位置:SN74LV2T74QPWRQ1 > SN74LV2T74QPWRQ1详情
SN74LV2T74QPWRQ1中文资料
SN74LV2T74QPWRQ1数据手册规格书PDF详情
1 Features
• AEC-Q100 qualified for automotive applications:
– Device temperature grade 1: -40°C to +125°C
– Device HBM ESD classification level 2
– Device CDM ESD classification level C4B
• Available in wettable flank QFN (WBQA) package
• Wide operating range of 1.8 V to 5.5 V
• Single-supply voltage translator (refer to LVxT
Enhanced Input Voltage):
– Up translation:
• 1.2 V to 1.8 V
• 1.5 V to 2.5 V
• 1.8 V to 3.3 V
• 3.3 V to 5.0 V
– Down translation:
• 5.0 V, 3.3 V, 2.5 V to 1.8 V
• 5.0 V, 3.3 V to 2.5 V
• 5.0 V to 3.3 V
• 5.5-V tolerant input pins
• Supports standard pinouts
• Up to 150 Mbps with 5-V or 3.3-V VCC
• Latch-up performance exceeds 250 mA
per JESD 17
2 Applications
• Convert a momentary switch to a toggle switch
• Hold a signal during controller reset
• Input slow edge-rate signals
• Operate in noisy environments
• Divide a clock signal by two
3 Description
The SN74LV2T74-Q1 contains two independent Dtype
positive-edge-triggered flip-flops. A low level at
the preset (PRE) input sets the output high. A low
level at the clear (CLR) input resets the output low.
Preset and clear functions are asynchronous and not
dependent on the levels of the other inputs. When
PRE and CLR are inactive (high), data at the data
(D) input meeting the setup time requirements is
transferred to the outputs (Q, Q) on the positive-going
edge of the clock (CLK) pulse. Clock triggering occurs
at a voltage level and is not directly related to the
rise time of the input clock (CLK) signal. Following
the hold-time interval, data at the data (D) input can
be changed without affecting the levels at the outputs
(Q, Q). The output level is referenced to the supply
voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and
5-V CMOS levels.
The input is designed with a lower threshold circuit to
support up translation for lower voltage CMOS inputs
(for example, 1.2 V input to 1.8 V output or 1.8 V input
to 3.3 V output). In addition, the 5-V tolerant input pins
enable down translation (for example, 3.3 V to 2.5 V
output).
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
原厂授权代理,专注军工、汽车、医疗、工业、新能源! |
|||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
||||
TI/德州仪器 |
25+ |
原厂封装 |
9999 |
||||
TI/德州仪器 |
25+ |
原厂封装 |
10280 |
||||
TI |
23+ |
N/A |
8000 |
只做原装现货 |
|||
TI |
23+ |
N/A |
7000 |
||||
TI |
25+ |
TSSOP |
2789 |
全新原装自家现货!价格优势! |
|||
TI |
2023+ |
3000 |
进口原装现货 |
||||
TI |
24+ |
TSSOP |
70 |
只做原装,欢迎询价,量大价优 |
|||
TI |
25+ |
TSSOP |
70 |
全新现货 |
SN74LV2T74QPWRQ1 资料下载更多...
SN74LV2T74QPWRQ1 芯片相关型号
- 396-012-500-201
- 396-012-500-202
- 396-012-500-203
- 396-012-500-204
- 396-012-500-207
- 396-012-500-601
- 396-012-500-602
- 396-012-500-603
- 396-012-500-604
- 396-012-500-801
- 396-012-500-802
- 396-012-500-803
- 396-012-500-804
- 745460400
- 745460801
- 745460813
- SN74LV2T74BQAR
- SN74LV2T74PWR
- SN74LV2T74QWBQARQ1
- XHP-8
- ZE05H-4DP-2H
- ZE05H-4DP-2HU
- ZE05H-4DP-2R
- ZE05H-4DP-2V
- ZE05H-4DS-2H
- ZE05H-4DS-2HU
- ZE05H-4DS-2R
- ZE05H-4P-2H
- ZE05H-4P-2V
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