1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1:

• 40°C to + 125°C, TA

– Device HBM ESD Classifiaction Level 2

– Device CDM ESD Classifcation Level C6

• Available in wettable flank QFN (WRKS) package

• 2 V to 5.5 V VCC operation

• Maximum tpd of 10.5 ns at 5 V

• Supports mixed-mode voltage operation on all

ports

• Ioff supports partial-power-down mode operation

• Latch-up performance exceeds 250 mA per JESD

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2 Applications

• Synchronize data to clock

• Simple memory - 8 bits

3 Description

The SN74LV273A-Q1 device is an octal positive-edge

triggered D-type flip-flop with shared direct active low

clear (CLR) input and clock (CLK).

Information at the data (D) inputs meeting the setup

time requirements is transferred to the (Q) outputs

on the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level

and is not related directly to the transition time of

the positive-going pulse. When CLK is at either the

high or low level or transitioning from a high level

to a low level, the D input has no effect at the

output. Information at the data (Q) outputs can be

asynchronously cleared with a low level input through

the clear (CLR) pin.