1 Features

• Ultra-low jitter BAW VCO based Ethernet clocks

– 42-fs typical/ 60-fs maximum RMS jitter at

312.5 MHz

– 47-fs typical/ 65-fs maximum RMS jitter at

156.25 MHz

• 3 high-performance Digital Phase Locked Loops

(DPLLs) with paired Analog Phase Locked Loops

(APLLs)

– Programmable DPLL loop bandwidth from 1

mHz to 4 kHz

– < 1-ppt DCO frequency adjustment step size

• 2 differential or single-ended DPLL inputs

– 1-Hz (1-PPS) to 800-MHz input frequency

– Digital holdover and hitless switching

• 16 differential outputs with programmable HSDS/

LVPECL, LVDS and HSCL output formats

– Up to 20 total frequency outputs when

configured with 6 LVCMOS frequency outputs

– 1-Hz (1-PPS) to 1250-MHz output frequency

with programmable swing and common mode

– PCIe Gen 1 to 6 compliant

• I2C or 3-wire/4-wire SPI interface

2 Applications

• Wired networking

– Inter/Intra DC interconnect

– Timing card

– Line card

– Fixed card (pizza box)

• SyncE (G.8262), SONET/SDH (Stratum 3/3E,

G.813, GR-1244, GR-253), IEEE 1588 PTP

secondary clock

• Jitter cleaning, wander attenuation and reference

clock generation for 56G/112G PAM-4 SerDes

• 100G-800G data center switches, core routers,

edge routers, WLAN

• Data center and enterprise computing

– Smart Network Interface Card (NIC)

• Optical Transport Networks (OTN G.709)

• Broadband fixed line access

• Industrial

– Test and measurement

– Medical imaging

3 Description

The LMK5B33216 is a high-performance network

synchronizer and jitter cleaner designed to meet the

stringent requirements of ethernet-based networking

applications with < 5-ns timing accuracy (class D).

The network synchronizer integrates three DPLLs to

provide hitless switching and jitter attenuation with

programmable loop bandwidth and no external loop

filters, maximizing flexibility and ease of use. Each

DPLL phase locks a paired APLL to a reference input.

APLL3 features ultra high performance PLL with TI's

proprietary Bulk Acoustic Wave (BAW) technology

and can generate 312.5 MHz output clocks with 42-

fs typical / 60-fs maximum RMS jitter irrespective

of the DPLL reference input frequency and jitter

characteristics. APLL2 and APLL1 provide options for

a second or third frequency and/or synchronization

domain.

Reference validation circuitry monitors the DPLL

reference clocks and performs a hitless switch

between them upon detecting a switchover event.

Zero delay and phase buildout may be enabled to

control the phase relationship from input to outputs.

The device is fully programmable through I2C or SPI

interface. The onboard EEPROM can be used to

customize system start-up clocks. The device also

features factory default ROM profiles as fallback

options.