1 Features

• 14-bit, single channel 250 and 500MSPS ADC

• Noise spectral density: -158.5dBFS/Hz

• Thermal Noise: 74.5dBFS

• Single core (non-interleaved) ADC architecture

• Power consumption:

– 435mW (500MSPS)

– 369mW (250MSPS)

• Aperture jitter: 75fs

• Buffered analog inputs

– Programmable 100 and 200Ω termination

• Input fullscale: 2Vpp

• Full power input bandwidth (-3dB): 1.4GHz

• Spectral performance (fIN = 70MHz, -1dBFS):

– SNR: 73.8dBFS

– SFDR HD2,3: 82dBc

– SFDR worst spur: 94dBFS

• Digital down-converters (DDCs)

– Up to four independent DDC

– Complex and real decimation

– Decimation: 2x, 4x to 32768x decimation

– 48-bit NCO phase coherent frequency hopping

• DDR/Serial LVDS interface

– 16-bit Parallel SDR, DDR LVDS for DDC

bypass

– Serial LVDS for decimation

– 32-bit output option for high decimation

2 Applications

• Software defined radio

• Spectrum analyzer

• Radar

• Spectroscopy

• Power amplifier linearization

• Communications infrastructure

3 Description

The ADC3548 and ADC3549 (ADC354x) is a 14-

bit, 250 and 500MSPS, single channel analog to

digital converter (ADC). The device is designed for

high signal-to-noise ratio (SNR) and delivers a noise

spectral density as low as -158.5dBFS/Hz.

The power efficient ADC architecture consumes

435mW at 500MSPS and provides power scaling with

lower sampling rates (369mW at 250MSPS).

The ADC354x includes a quad band digital downconverter

(DDC) supporting wide band decimation by

2 to narrow band decimation by 32768. The DDC

uses a 48-bit NCO which supports phase coherent

and phase continuous frequency hopping.

The ADC354x is outfitted with a flexible LVDS

interface. In decimation bypass mode, the device

uses a 14-bit wide parallel SDR or DDR LVDS

interface. When using decimation, the output data is

transmitted using a serial LVDS interface reducing the

number of lanes needed as decimation increases. For

high decimation rates, the output resolution can be

increased to 32-bit.