Toshiba CMOS digital integrated circuit silicon monolithic

OCTAL D-TYPE FLIP-FLOP The TC74AC377 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation

CMOS Digital Integrated Circuit Silicon Monolithic Octal D-Type Flip-Flop

OCTAL D-TYPE FLIP-FLOP The TC74AC377 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation

74AC CMOS logic IC series

Toshiba CMOS digital integrated circuit silicon monolithic

OCTAL D-TYPE FLIP-FLOP The TC74AC377 is an advanced high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

Octal D-Type Flip-Flop with Clock Enable

General Description The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one

Octal D-Type Flip-Flop with Clock Enable

文件：426.64 Kbytes Page：13 Pages

Octal D-Type Flip-Flop with Clock Enable

文件：426.64 Kbytes Page：13 Pages