3-STATE HEX BUFFERS

DESCRIPTION These devices are high-speed Hex Buffers with 3- state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D) paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW. When

Hex 3-STATE Buffer/Bus Driver

General Description This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the d

Hex 3-STATE Buffer/Bus Driver

General Description This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the d

Hex 3-STATE Buffer/Bus Driver

General Description This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the d

Hex Bus Drivers(with three-state outputs)

● Quadrupie 2-Input Positive NAND Gates ● Quadruple 2-Input Positive NAND Gates (with Open Collector Output) (Continue....)

Hex TRI-STATE Buffers

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