Features

 Highly-integrated, 4 PLL clock

multiplier/jitter attenuator

 Four independent DSPLLs support

any-frequency synthesis and jitter

attenuation

 8 inputs/8 outputs

 Each DSPLL can generate any

frequency from 2 kHz to 808 MHz

from a 2 kHz to 710 MHz input

 350 fs rms (12 kHz– 20 MHz) and

410 fs rms (50 kHz–80 MHz)

typical

 Meets ITU-T G.8251 and Telcordia

GR-253-CORE OC-192 jitter

specifications

 Programmable loop bandwidth:

60 Hz to 8 kHz

 Faster lock acquisition compared to

the Si5374: <1.2 s

 For a very low-loop BW version, see

the Si5374

 Supports all ITU G.709 and any

custom FEC ratios (239/237,

255/238, 255/237, 255/236, 253/226)

 Integrated loop filter with

programmable bandwidth

 Simultaneous free-run and

synchronous operation

 Automatic/manual hitless input clock

switching

 Selectable output clock signal format

(LVPECL, LVDS, CML, CMOS)

 LOL and interrupt alarm outputs

 I2C programmable

 Single 1.8 V ±5 or 2.5 V ±10

operation with high PSRR on-chip

voltage regulator

 10x10 mm PBGA