Features

 Highly integrated, 4–PLL clock

multiplier/jitter attenuator

 Four independent DSPLLs

support any-frequency synthesis

and jitter attenuation

 Four inputs/four outputs

 Each DSPLL can generate any

frequency from 2 kHz to

808 MHz from a 2 kHz to

710 MHz input

 Ultra-low jitter clock outputs:

350 fs rms (12 kHz– 20 MHz)

and 410 fs rms (50 kHz–80 MHz)

typical

 Meets ITU-T G.8251 and

Telcordia GR-253-CORE OC-192

jitter specifications

 Integrated loop filter with

programmable bandwidth as low

as 60 Hz

 Simultaneous free-run and

synchronous operation

 Automatic/manual hitless input

clock switching

 Selectable output clock signal

format (LVPECL, LVDS, CML,

CMOS)

 LOL and interrupt alarm outputs

 I2C programmable

 Single 1.8 V ±5 or 2.5 V ±10

operation with high PSRR onchip

voltage regulator

 10x10 mm PBGA