5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK

DESCRIPTION The SY10EP51V is a D flip-flop with reset and differential clock. The device is pin and functionally equivalent to the EL51 device. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when CLK is LOW and is transferred to the sl

5V/3.3V D FLIP-FLOP WITH RESET AND DIFFERENTIAL CLOCK

文件：575.96 Kbytes Page：8 Pages

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock

Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. Features • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes Page：11 Pages

ECL D Flip-Flop with Reset and Differential Clock

文件：156.53 Kbytes Page：11 Pages

3.3V / 5V ECL D Flip?묯lop with Reset and Differential Clock

文件：155.07 Kbytes Page：11 Pages