封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK GEN /2 /4/6 3.3/5V 20SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK GEN /2 /4/6 3.3/5V 20SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff

5V/3.3V 첨2, 첨4/6 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL38/L are low skew ÷2, ÷4/6 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a diff