1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

3.3V 1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be u

3.3V 1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be u

3.3V 1:4 CLOCK

FEATURES 3.3V power supply 50ps output-to-output skew Low power Synchronous enable/disable Multiplexed clock input 75KΩ internal input pull-down resistors ESD protection of 2000V Available in 16-pin SOIC package DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC design

3.3V 1:4 CLOCK

FEATURES 3.3V power supply 50ps output-to-output skew Low power Synchronous enable/disable Multiplexed clock input 75KΩ internal input pull-down resistors ESD protection of 2000V Available in 16-pin SOIC package DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC design

3.3V 1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be u

3.3V 1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be u

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

1:4 CLOCK DISTRIBUTION

DESCRIPTION The SY10/100EL15 are low skew 1:4 clock distribution chips designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to

3.3V 1:4 CLOCK DISTRIBUTION

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Buffers

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER 2:4 16SOIC 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 2:4 16SOIC 集成电路（IC） 时钟缓冲器，驱动器

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

3.3V 1:4 CLOCK DISTRIBUTION

文件：60.63 Kbytes Page：5 Pages

1:4 Clock Distribution Chip

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB

5V ECL 1:4 Clock Distribution Chip

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5V ECL 1:4 Clock Distribution Chip

文件：147.52 Kbytes Page：8 Pages

5V ECL 1:4 Clock Distribution Chip

文件：163.63 Kbytes Page：8 Pages

5V ECL 1:4 Clock Distribution Chip

文件：147.52 Kbytes Page：8 Pages