6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

6-BIT 2:1 MUX-LATCH

文件：66.99 Kbytes Page：4 Pages

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

6-BIT 2:1 MUX-LATCH

文件：66.99 Kbytes Page：4 Pages

6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2