6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

Multiplexers Products

The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. The two external latch-enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the six latches. When both LEN1 a ·750ps max. LEN to output\n·Extended 100E VEE range of -4.2V to -5.5V\n·700ps max. D to output\n·Single-ended outputs\n·Asynchronous Master Reset\n·Dual latch-enables\n·Fully compatible with industry standard 10KH, 100K ECL levels\n·Internal 75KΩ input pulldown resistors\n·Fully compatible with Moto;

6-BIT 2:1 MUX-LATCH

文件：66.99 Kbytes Page：4 Pages

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

6-BIT 2:1 MUX-LATCH

DESCRIPTION The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. FEATURES ■ 750ps max. LEN to output ■ Extended 100E VEE range of –4.2V to –5.5V ■ 700ps max. D to output ■ Single-ended outputs ■ As

6-BIT 2:1 MUX-LATCH

文件：66.99 Kbytes Page：4 Pages

6-BIT 2:1 MUX-LATCH

文件：66.99 Kbytes Page：4 Pages

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC MULTIPLEXER 6 X 2:1 28PLCC 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：28-LCC（J 形引线） 包装：管件 描述：IC MULTIPLEXER 6 X 2:1 28PLCC 集成电路（IC） 信号开关，多路复用器，解码器

6-BIT 2:1 MUX-LATCH

Description The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single−ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2