Medium-density access line, ARM®-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

Features  Core: ARM® 32-bit Cortex® -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 to 128 Kbytes of Flash memory – 10 to 16 Kbytes of SRAM  Clock, reset an

Medium-density access line, ARM®-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

Features  Core: ARM® 32-bit Cortex® -M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 to 128 Kbytes of Flash memory – 10 to 16 Kbytes of SRAM  Clock, reset an

Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

文件：1.23691 Mbytes Page：85 Pages

Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

文件：999.99 Kbytes Page：81 Pages

Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

文件：1.23691 Mbytes Page：85 Pages

Medium-density access line, ARM-based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces

文件：999.99 Kbytes Page：81 Pages