Super high dense cell design for low RDS(ON).

STU412S TO-252 Single-N STU420S TO-252 Single-N STU442S TO-252 Single-N STU410S TO-252 Single-N STU456A TO-252 Single-N STU456S TO-252 Single-N STU448S TO-252 Single-N STU466S TO-252 Single-N STU446S TO-252 Single N STU432L TO-252 Single N STU438A TO-252 Single-N STU458S TO-252 Single N

Mosfets

Integrated Circuit NMOS, 1K Static RAM (SRAM), 350ns

Description: The NTE2101 is a high–speed 1024 x 1 bit static random access read/write memory in a 16–Lead DIP type package designed using N–Channel depletion mode silicon gate technology. Static storage cells eliminate the need for clock or refresh circuitry. Low threshold silicon gate N–Cha

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages

SYSTEM RESET IC

文件：314.14 Kbytes Page：11 Pages