SIPMOS Small-Signal Transistor

SIPMOS® Small-Signal Transistor ● VDS − 60 V ● ID − 0.18 A ● RDS(on) 10 Ω ● P channel ● Enhancement mode

SIPMOS Small-Signal Transistor

SIPMOS ® Small-Signal Transistor • P channel • Enhancement mode • Logic Level • VGS(th) = -1.0 -2.0V

SIPMOS Small-Signal Transistor

SIPMOS® Small-Signal Transistor

● VDS − 60 V\n● ID − 0.18 A\n● RDS(on) 10 Ω\n● P channel\n● Enhancement mode

SIPMOS Small-Signal Transistor

SIPMOS® Small-Signal Transistor ● VDS − 60 V ● ID − 0.18 A ● RDS(on) 10 Ω ● P channel ● Enhancement mode

SIPMOS Small-Signal Transistor

SIPMOS ® Small-Signal Transistor • P channel • Enhancement mode • Logic Level • VGS(th) = -1.0 -2.0V

丝印代码：T50*；P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high inpu

N-Channel Enhancement-Mode MOS Transistors

Features ● Zener Diode Input Protected ● Low On-Resistance: 3 Ω ● Ultralow Threshold: 1.2 V ● Low Input Capacitance: 38 pF ● Low Input and Output Leakage Benefits ● Extra ESD Protection ● Low Offset Voltage ● Low-Voltage Operation ● High-Speed, Easily Driven ● Low Error Voltage Appli

N-Channel Enhancement-Mode MOS Transistors

Features ● Zener Diode Input Protected ● Low On-Resistance: 3 Ω ● Ultralow Threshold: 1.2 V ● Low Input Capacitance: 38 pF ● Low Input and Output Leakage Benefits ● Extra ESD Protection ● Low Offset Voltage ● Low-Voltage Operation ● High-Speed, Easily Driven ● Low Error Voltage Appli

N-Channel Enhancement-Mode Vertical DMOS FETs

文件：31.44 Kbytes Page：4 Pages