28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing

符合 JEDEC SSTE32882 标准且具有地址奇偶校验的 28 位至 56 位寄存缓冲器

28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

文件：498.91 Kbytes Page：9 Pages

28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing

28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

1FEATURES • JEDEC SSTE32882 • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing

28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver

文件：498.91 Kbytes Page：9 Pages

封装/外壳：176-TFBGA 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC REGSTR BUFF 28-56BIT 176NFBGA 集成电路（IC） 专用逻辑器件