3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Members of the Texas Instruments WidebusE Family Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Members of the Texas Instruments WidebusE Family Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

General Description The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data in

Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

General Description The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data in

Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

General Description The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data in

Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

General Description The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data in