10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

FEATURES · Operates From 1.65 V to 3.6 V · Inputs Accept Voltages to 5.5 V · Max tpd of 6.7 ns at 3.3 V · Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C · Ioff Supports Partial-Power-Down Mode Oper

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC 10BIT BUS INT D LATCH 24-SOIC 集成电路（IC） 锁存器

10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

文件：843.17 Kbytes Page：17 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC D-TYPE LATCH SGL 3-ST 24SOIC 集成电路（IC） 锁存器

10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

文件：136.2 Kbytes Page：9 Pages

10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with the JEDEC

10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with the JEDEC

10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with the JEDEC

10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with the JEDEC