丝印代码：LVC74A；SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

丝印代码：LVC74A；SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

丝印代码：LVC74A；SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

丝印代码：LVC74A；SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

丝印代码：LVC74A；SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：516.539 Kbytes Page：17 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：814.84 Kbytes Page：19 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：661.44 Kbytes Page：19 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：1.2074 Mbytes Page：27 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：661.44 Kbytes Page：19 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：516.539 Kbytes Page：17 Pages

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

文件：814.84 Kbytes Page：19 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c