SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

1 Features • Operate from 1.65V to 3.6V • Inputs accept voltages to 5.5V • Maximum tpd of 5.2ns at 3.3V • Typical VOLP (output ground bounce) 2V at VCC = 3.3V, TA = 25°C • Latch-up performance exceeds 250mA per JESD 17

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

Dual D-type flip-flop with set and reset; positive-edge trigger