OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：914.67 Kbytes Page：25 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：1.16987 Mbytes Page：30 Pages

封装/外壳：20-SOIC（0.209"，5.30mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：1.16987 Mbytes Page：30 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：914.67 Kbytes Page：25 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：1.16987 Mbytes Page：30 Pages

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC574A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. FEATURES • 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic • Supply voltage range of 2.7V to 3.6V • Complies with JEDEC

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

1. General description The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS

文件：478.34 Kbytes Page：11 Pages

Low-Voltage CMOS Octal Buffer Flow Through Pinout

文件：101.31 Kbytes Page：10 Pages

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger 3-state

文件：142.99 Kbytes Page：19 Pages