OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：633.9 Kbytes Page：21 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：891.65 Kbytes Page：23 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：982.26 Kbytes Page：26 Pages

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：标准 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：982.26 Kbytes Page：26 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：633.9 Kbytes Page：21 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：891.65 Kbytes Page：23 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：982.26 Kbytes Page：26 Pages

Low-Voltage CMOS Octal Buffer

Low-Voltage CMOS Octal D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC374A is a high performance, non−inverting octal D−type flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE)

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

Low-Voltage CMOS Octal D-Type Flip-Flop

文件：101.96 Kbytes Page：10 Pages