SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

1 Features • Available in the Texas Instruments NanoFree™ package • Supports 5-V VCC operation • Inputs accept voltages to 5.5-V • Supports down translation to VCC • Maximum tpd of 5.9-ns at 3.3-V • Low power consumption, 10-μA maximum ICC • ±24-mA output drive at 3.3-V • Typical VOLP (ou

SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

文件：1.32742 Mbytes Page：24 Pages

Available in the Texas Instruments NanoFree??Package

文件：811.21 Kbytes Page：21 Pages

封装/外壳：8-XFDFN 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 1BIT 8X2SON 集成电路（IC） 触发器

SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

1 Features • Available in the Texas Instruments NanoFree™ package • Supports 5-V VCC operation • Inputs accept voltages to 5.5-V • Supports down translation to VCC • Maximum tpd of 5.9-ns at 3.3-V • Low power consumption, 10-μA maximum ICC • ±24-mA output drive at 3.3-V • Typical VOLP (ou

SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

1 Features • Available in the Texas Instruments NanoFree™ package • Supports 5-V VCC operation • Inputs accept voltages to 5.5-V • Supports down translation to VCC • Maximum tpd of 5.9-ns at 3.3-V • Low power consumption, 10-μA maximum ICC • ±24-mA output drive at 3.3-V • Typical VOLP (ou

SN74LVC1G74 Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

1 Features • Available in the Texas Instruments NanoFree™ package • Supports 5-V VCC operation • Inputs accept voltages to 5.5-V • Supports down translation to VCC • Maximum tpd of 5.9-ns at 3.3-V • Low power consumption, 10-μA maximum ICC • ±24-mA output drive at 3.3-V • Typical VOLP (ou

Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

Single D-type flip-flop with set and reset; positive edge trigger

DESCRIPTION The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and comp

Single D-type flip-flop with set and reset; positive edge trigger

Single D-type flip-flop with set and reset; positive edge trigger

Single D-type flip-flop with set and reset; positive edge trigger