SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR

文件：545.67 Kbytes Page：14 Pages

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th