SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

Single D-Type Flip-Flop With Asynchronous Clear

文件：1.18533 Mbytes Page：28 Pages

SINGLE D-TYPE DFLIP FLOP WITH ASYNCHRONOUS CLEAR

文件：226.73 Kbytes Page：12 Pages

封装/外壳：SOT-23-6 功能：复位 包装：管件 描述：IC FF D-TYPE SNGL 1BIT SOT23-6 集成电路（IC） 触发器

SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear

1 Features 1• Available in the Texas Instruments NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports Down Translation to VCC • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Live Inse

Single D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

Single D-type flip-flop with reset; positive-edge trigger

General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. Th